Models and Methods for HW/SW Intellectual Property Interfacing

This paper focuses on the problem of enabling system companies to quickly integrate IPs from di erent sources, and adapt them to di erent manufacturing technologies. An evolutionary approach from current methodologies is possible with appropriate and extensive CAD support. We cover the main aspects of interfacing Intellectual Property, both in hardware and software form, in an embedded system design context. In particular, we review the main approaches to speci cation, synthesis and validation of interfaces that have appeared in the literature. From the speci cation viewpoint, we illustrate the main protocol and timing constraint speci cation models. From the synthesis and optimization viewpoint, we review software and hardware generation, as well as time-driven interface scheduling techniques. From the veri cation viewpoint, we discuss various strategies for hardware/software co-simulation, with special attention to the interface layer. Finally, we consider the growing importance of formal veri cation in this domain, and outline the main techniques for interface protocol veri cation.